Test MP+dmb.sy+pos-[fr-rf]-pos-addr-rfi

AArch64 MP+dmb.sy+pos-[fr-rf]-pos-addr-rfi
"DMB.SYdWW Rfe PosRR FrLeave RfBack PosRR DpAddrdW Rfi Fre"
Cycle=Rfi Fre DMB.SYdWW Rfe PosRR FrLeave RfBack PosRR DpAddrdW
Relax=
Safe=Rfi Rfe Fre PosRR DMB.SYdWW DpAddrdW [FrLeave,RfBack]
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr Rf
Orig=DMB.SYdWW Rfe PosRR FrLeave RfBack PosRR DpAddrdW Rfi Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X7=x;
2:X1=y;
}
 P0          | P1                  | P2          ;
 MOV W0,#2   | LDR W0,[X1]         | MOV W0,#2   ;
 STR W0,[X1] | LDR W2,[X1]         | STR W0,[X1] ;
 DMB SY      | LDR W3,[X1]         |             ;
 MOV W2,#1   | LDR W4,[X1]         |             ;
 STR W2,[X3] | EOR W5,W4,W4        |             ;
             | MOV W6,#1           |             ;
             | STR W6,[X7,W5,SXTW] |             ;
             | LDR W8,[X7]         |             ;
Observed
    y=1; x=1; 1:X8=1; 1:X4=2; 1:X3=2; 1:X2=0; 1:X0=2;